1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and, more particularly, to a data receiver of a semiconductor integrated circuit.
2. Related Art
As shown in FIG. 1, a conventional multi-level signaling data receiver of a semiconductor integrated circuit includes first to fourth receiver units 10 to 40. The first to fourth receiver units 10 to 40 detect and amplify multi-level differential data signals ‘INP’ and ‘INN’, which have been input through a pad PAD and a pad bar PADB, according to clock signals ‘CLK000’, ‘CKL090’, ‘CLK180’, and ‘CLK 270’ with a predetermined phase difference.
Since the first and fourth receiver units 10 to 40 have the same structure, the structure of the first receiver unit 10 will be representatively described below with respect to FIG. 2. As shown in FIG. 2, the first receiver unit 10 includes a high-level detector 11, a mid-level detector 12, and a low-level detector 13, which include their respective amplifiers and latches, and an encoder 14.
The high-level detector 11 outputs a high-level signal if the levels of the differential data ‘INP’ and ‘INN’ exceed a level of a first reference voltage HR. The mid-level detector 12 outputs a high-level signal if the levels of the differential data ‘INP’ and ‘INN’ exceed a level of a second reference voltage MR. The low-level detector 13 outputs a high-level signal if the levels of the differential data ‘INP’ and ‘INN’ exceed a level of a third reference voltage LR. The encoder 14 encodes output signals of the high-level detector 11, the mid-level detector 12, and the low-level detector 13.
As opposed to a conventional two level scheme for processing data using, i.e., ‘1’ and ‘0’, a multi-level signaling scheme processes data using four levels, i.e., ‘00’, ‘01’, ‘10’, and ‘11’.
According to a conventional two level scheme for processing data, data is processed such that it has a level higher than or lower than a level of a specific reference voltage and then the data is transmitted. A receiver unit compares the level of the data with the level of the specific reference voltage to obtain the data of ‘1’ or ‘0’.
Meanwhile, as shown in FIG. 3A, in a conventional multi-level signaling scheme, data is processed to such that it has a level belonging to one of four-step sections, which are obtained based on the first to third reference voltages HR, MR, and LR, and then the data is transmitted. As shown in FIG. 3B, a receiver unit, or more specifically the high-level detector 11, the mid-level detector 12, and the low-level detector 13 of the first to fourth receiver units 10 to 40 output high-level signals or low-level signals through the comparison with the first to third reference voltages HR, MR, and LR, and obtain data of ‘00’, ‘01’, ‘10’, or ‘11’ by encoding the output signals in the encoder 14.
As the data rate of conventional semiconductor integrated circuits gradually increases, the design margin for a conventional data receiver is gradually decreasing. One of the main factors leading to the decrease in design margin is “inter symbol interference”. The inter symbol interference can occur because signal loss increases as the frequency of data transmission increases.
When a multi-level signaling scheme is used the signal loss can be even worse, since a low voltage level is divided into several sections. Thus, the design margin of the data receiver is even worse due to inter symbol interference.
Accordingly, a multi-level data receiver additionally requires an equalizer to compensate for the signal loss.
A feed-forward equalization (FFE) scheme and a decision-feedback equalization (DFE) scheme can be used as representative schemes for constructing the equalizer. Example, FFE and the DFE schemes are seen in “IEEE JSSC, Vol.35, No.5., May 2000, pp.757-764” and “IEEE JSSC, Vol. 40, No. 4., April 2005, pp.1012-1026, respectively. However, when a FFE or DFE scheme is used, the circuit structure can become very complex. Moreover, a FFE scheme can amplify noise as well as the data, adding to the problems.